March 96, from the digest of technical papers of the 1996 IEEE ICCE: 0-7803-3029
Abstract: This paper describes a one-chip signal processing
LSI for a MiniDisc recorder. The LSI is fabricated by a 0.4um CMOS
process and consumes only 100mW when used with 2.8V power supply.
This chip is presumed to be in the MDS-JE500/S37 and given the nomenclature CXD-2650, based upon the following information from the 9/96 issues of the German Stereo magazine:
In contrast to prior models, which used separate chips for data- reduction, servo- mechanism- controlling and sample- rate- conversion, the new MDS-JE500 contains only one chip for this purposes, named CXD-2650, which is much cheaper than the former solution
Major improvements have be done to calculation accuracy. The formula used for ATRAC 3.0 and 3.5 of 24/16 Bit for word- and coefficiency- length was expanded to 24/24, which positivly affects the reproduction quality. No change could be made to the noise reduction, because ATRAC 3.5 worked already in 20Bit Resolution.
Chip Functions: The LSI in this report combines all the digital signal processing circuits required for an MD recorder, including the shock resistant memory. Sony's previous chip set required four chips to achieve this. Other than this chip, only a micro-controller, bipolar RF amp, AD/DA converter a few driver chips are needed.
The LSI includes the subsections shown below:
When the data remaining in the Shock Resistant Memory reaches its low-water mark, the stopped functions are reenabled, requiring a track-jump, focus-search and spindle-kick, all of which consume power. Starting the spindle motor from a dead stop is a particularly heavy load and so to avoid it the spindle is kept rotating even while disc reading is suspended. However since the laser diode is off there is no CLV (Constant Linear Velocity) spindle servo error signal available for speed control, so the LSI circuit supports CAV (Constant Angular Velocity) spindle servo mode, which uses the frequency generator of the spindle servo as the error signal.
By placing the Shock Resistant Memory on-chip, substantially smaller (and lower power) drivers can be used for the RAM address and data lines, further reducing power consumption. At 2.8V the chip consumes 100mW, but it can be run on supply voltages down to 2.4V, thus allowing even lower power consumption.
Audio Quality: Sony's design requirement was that the chip's audio quality be sufficiently high to allow its use in a wide range of MD units, from portable players to home decks. A 24-bit customized DSP is used as the ATRAC encoder/decoder providing high computational accuracy. It consumes very little power, running at a clock rate as low as 11.3 MHz. The ATRAC encoder/decoder specifications are: THD+N: 0.0018% (1kHz, 0dB), Dynamic range: 112dB. The on-chip asynchronous sampling rate converter's specifications are: THD+N: 0.0008% (1kHz, 0dB).
LSI Specifications: The LSI Chip itself is a 0.4um CMOS 3-layer AL device packaged in a 100pin 14 x 14mm LQFP (Low Profile Quad Flat Pack), operating at 2.4-3.6V, and dissipating 100mW @ 2.8V.